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? semiconductor components industries, llc, 2013 may, 2013 ? rev. 2 1 publication order number: MC74HC160A/d MC74HC160A presettable counters high ? performance silicon ? gate cmos the MC74HC160A is identical in pinout to the ls160. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hc160a is a programmable bcd counters with asynchronous reset input. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 234 fets or 58.5 equivalent gates ? these are pb ? free devices figure 1. logic diagram pin 16 = v cc pin 8 = gnd 11 12 13 14 q0 q1 q2 q3 15 ripple carry out bcd outputs 3 4 5 6 p0 p1 p2 p3 2 clock reset load enable p enable t count enables present data inputs device count mode reset mode hc160 bcd asynchronous http://onsemi.com marking diagrams soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 1 16 1 16 hc160ag awlyww hc 160a alyw 1 16 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information (note: microdot may be in either location) pin assignment 1 16 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 reset p0 clock gnd q1 q0 ripple carry out v cc p1 p2 p3 enable p q2 q3 enable t load
MC74HC160A http://onsemi.com 2 function table inputs outputs clock reset* load enable p enable t q l x x x reset h l x x load preset data h h h h count h h l x no count h h x l no count *hc160 is an asynchronous reset device. h = high level l = low level x = don?t care maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to +7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic or ceramic dip? soic package? 750 500 mw t stg storage temperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recomme nded operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 +125 c t r , t f input rise and fall time v cc = 2.0 v (figure 3) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
MC74HC160A http://onsemi.com 3 dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c v ih minimum high ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 m |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 m |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a
MC74HC160A http://onsemi.com 4 ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle)* (figures 3 and 8) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 mhz t plh maximum propagation delay, clock to q (figures 3 and 8) 2.0 4.5 6.0 170 34 29 215 43 37 255 51 43 ns t phl 2.0 4.5 6.0 205 41 35 255 51 43 310 62 53 t phl maximum propagation delay, reset to q (hc160a only) (figures 4 and 8) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns t plh maximum propagation delay, enable t to ripple carry out (figures 5 and 8) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns t phl 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 t plh maximum propagation delay, clock to ripple carry out (figures 3 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t phl 2.0 4.5 6.0 215 43 37 270 54 46 325 65 55 t phl maximum propagation delay, reset to ripple carry out (hc160a only) (figures 4 and 8) 2.0 4.5 6.0 220 44 37 275 55 47 330 66 56 ns t tlh , t thl maximum output transition time, any output (figures 3 and 8) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance ? 10 10 10 pf *applies to noncascaded/nonsynchronously clocked configurations only. with synchronously cascaded counters, (1) clock to ripple carry out propagation delays, (2) enable t or enable p to clock setup times, and (3) clock to enable t or enable p hold times determine f max . however, if ripple carry out of each stage is tied to the clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable. see applications information in this data sheet. c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 60 *used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
MC74HC160A http://onsemi.com 5 timing requirements (input t r = t f = 6 ns) ????? ????? ????? ????? symbol ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ?????????? ?????????? ??? ??? ??? ??? ???? ???? ???? ? 55 to 25 c ???? ???? ???? 85 c ???? ???? ???? 125 c ????? ????? ????? t su ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ????? ????? ????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ???
MC74HC160A http://onsemi.com 6 function description the hc160a is a programmable 4 ? bit synchronous counters that feature parallel load, synchronous or asynchronous reset, a carry output for cascading, and count ? enable controls. the hc160a is a bcd counter with asynchronous reset. inputs clock (pin 2) the internal flip ? flops toggle and the output count advances with the rising edge of the clock input. in addition, control functions, such as loading occur with the rising edge of the clock input. preset data inputs p0, p1, p2, p3 (pins 3, 4, 5, 6) these are the data inputs for programmable counting. data on these pins may be synchronously loaded into the internal flip ? flops and appear at the counter outputs. p0 (pin 3) is the least ? significant bit and p3 (pin 6) is the most ? significant bit. outputs q0, q1, q2, q3 (pins 14, 13, 12, 11) these are the counter outputs (bcd or binary). q0 (pin 14) is the least ? significant bit and q3 (pin 11) is the most ? significant bit. ripple carry out (pin 15) when the counter is in its maximum state (1001 for the bcd counters or 1111 for the binary counters), this output goes high, providing an external look ? ahead carry pulse that may be used to enable successive cascaded counters. ripple carry out remains high only during the maximum count state. the logic equation for this output is: ripple carry out = enable t q0 q1 q2 q3 for bcd counters control functions resetting a low level on the reset pin (pin 1) resets the internal flip ? flops and sets the outputs (q0 through q3) to a low level. the hc160a resets asynchronously. loading with the rising edge of the clock, a low level on load (pin 9) loads the data from the preset data input pins (p0, p1, p2, p3) into the internal flip ? flops and onto the output pins, q0 through q3. the count function is disabled as long as load is low. although the hc160a is a bcd counters, they may be programmed to any state. if they are loaded with a state disallowed in bcd code, they will return to their normal count sequence within two clock pulses (see the output state diagram). count enable/disable these devices have two count ? enable control pins: enable p (pin 7) and enable t (pin 10). the devices count when these two pins and the load pin are high. the logic equation is: count enable = enable p enable t load the count is either enabled or disabled by the control inputs according to table 1. in general, enable p is a count ? enable control; enable t is both a count ? enable and a ripple ? carry output control. table 1. count enable/disable control inputs result at outputs load enable p enable t q0 ? q3 ripple carry out h h h count high when q0 ? q3 are max- imum* l h h no count x l h no count high when q0 ? q3 are max- imum* x x l no count l *q0 through q3 are maximum for the hc160a when q3 q2 q1 q0 = 1001. 01234 5 6 7 8 9 10 11 12 13 14 15 figure 2. output state diagrams hc160a bcd counters
MC74HC160A http://onsemi.com 7 switching waveforms figure 3. figure 4. figure 5. figure 6. figure 7. test circuit figure 8. t r t f v cc gnd t thl t tlh any output 90% 50% 10% 90% 50% 10% clock t plh t phl 50% t phl v cc gnd v cc gnd any output clock reset 50% 50% t rec t r t f v cc gnd t phl t plh 90% 50% 10% 90% 50% 10% t thl t tlh enable t ripple carry out inputs p0, p1, p2, p3 50% v cc gnd v cc gnd gnd 50% 50% load clock v cc gnd v cc gnd enable t or enable p 50% 50% clock *includes all probe and jig capacitance c l * test point device under test output v cc t w 1/fmax t w valid t su t h t su t h t rec valid t su t h
MC74HC160A http://onsemi.com 8 MC74HC160A bcd counter with asynchronous reset p0 p1 p2 p3 enable p enable t reset clock load r c t0 r c c load load p0 q0 q0 q1 q2 q3 ripple carry out v cc = pin 16 gnd = pin 8 14 the flip ? flops shown in the circuit diagrams are toggle ? enable flip ? flops. a toggle ? enable flip ? flop is a combination of a d flip ? flop and a t flip ? flop. when loading data from preset inputs p0, p1, p2, and p3, the load signal is used to disable the toggle input (tn) of the flip ? flop. the logic level at the pn input is then clocked to the q output of the flip ? flop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flip ? flop low. c load load q0 q1 q1 q2 q2 q3 q3 t1 r c c load load p1 t2 r c c load load p2 t3 r c c load load p3 13 12 11 15 3 4 5 6 7 10 1 2 3
MC74HC160A http://onsemi.com 9 figure 9. MC74HC160A timing diagram sequence illustrated in waveforms: 1. reset outputs to zero. 2. preset to bcd seven. 3. count to eight, nine, zero, one, two, and three. 4. inhibit. reset (hc160a) load p0 p1 p2 p3 clock (hc160a) clock (hc162a) enable p enable t q0 q1 q2 q3 ripple carry out (asynchronous) 789012 3 reset load count enables outputs preset data inputs inhibit count
MC74HC160A http://onsemi.com 10 inputs outputs to more significant stages load h = count l = disable h = count l = disable reset clock load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load reset clock enable p enable t typical applications cascading figure 10. n ? bit synchronous counters note: when used in these cascaded configurations the clock f max guaranteed limits may not apply. actual performance will depend on number of stages. this limitation is due to set up times between enable (port) and clock. figure 11. nibble ripple counter load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out inputs outputs inputs outputs inputs inputs inputs outputs outputs outputs to more significant stages load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out ordering information device package shipping ? MC74HC160Adg soic ? 16 (pb ? free) 48 units / rail MC74HC160Adr2g soic ? 16 (pb ? free) 2500 tape & reel MC74HC160Adtg tssop ? 16* 96 units / rail MC74HC160Adtr2g tssop ? 16* 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
MC74HC160A http://onsemi.com 11 package dimensions tssop ? 16 dt suffix case 948f ? 01 issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
MC74HC160A http://onsemi.com 12 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 MC74HC160A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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